1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device that reads out stored data at high speed.
2. Description of the Invention
A DRAM (Dynamic Random Access Memory) which is a conventional semiconductor memory device will be described hereinafter with reference to FIG. 23 which is a block diagram showing a structure thereof.
Referring to FIG. 23, a semiconductor memory device includes readout circuits RR0a-RR3a, RR0b-RR3b, RR0c-RR3c, RR0d-RR3d, memory cell array M0a-M3a, M0b-M3b, M0c-M3c, M0d-M3d, row decoders RDa, RDb, column decoders CDa-CDd, selectors SEPa-SEPd, output circuits DQPa-DQPd, a control circuit CCP, a row address buffer RB, a column address buffer RB, and a predecoder PD.
An externally applied address signal AD is supplied to row address buffer RD and column address buffer CB. Row address buffer RB receives an address signal AD to output a row address signal RAi. Column address buffer CB receives an address signal AD to output a column address signal CAi.
A column address signal CAi is supplied to predecoder PD. Predecoder PD receives a column address signal CAi to output a predecode signal Yi (i=0-23). Predecode signals Y0-Y3, and Y7 are applied to readout circuits RR0a-RR0d. Predecode signals Y0-Y3 and Y6 are applied to readout circuits RR1a-RR1d. Predecode signals Y0-Y3 and Y5 are applied to readout circuits RR2a-RR2d. Predecode signals Y0-Y4 are applied to readout circuits RR3a-RR3d. Predecode signals Y0-Y3 serve to select data input and output lines IO and/IO in memory cell arrays M0a-M3a, M0b-M3b, M0c-M3c and M0d-M3d corresponding to readout circuits RR0a-RR3a, RR0b-RR3b, RR0c-RR3c, and RR0d-RR3d. Predecode signals Y4-Y7 serve to select a readout circuit and a memory cell array. Predecode signals Y0-Y3 are applied to selectors SEPa-SEPd. Predecode signals Y8-Y23 are applied to column decoders CDa-CDd.
Externally applied row address strobe signal/RAS, a column address strobe signal/CAS and an address signal AD are applied to control circuit CCP. Control circuit CCP responds to each input signal to output an address change detection signal ATD, a data select control signal .phi..sub.D, a differential amplifier activation signal PAE, a data transfer control signal .phi..sub.TP, and an output buffer activation signal .phi..sub.E.
A row address signal RAi is applied from row address buffer RB to row decoders RDa and RDb. Row decoders RDa and RDb respond to row address signal RAi to activate a predetermined word line in a memory cell array. Column decoders CDa-CDd respond to predecode signals Y8-Y23 to select a predetermined bit line in a memory cell array. Data of a memory connected to the selected word line and bit line are provided to a readout circuit.
Readout circuits RR0a-RR3a are connected to a selector SEPa via readout data lines RD0a-RD3a. Selector SEPa selects a readout data line selected by predecode signals Y0-Y3 from readout data lines RD0a-RD3a to provide the signal of the selected readout line to output circuit DQPa via an output data bus RBUSa. Output circuit DQPa latches the input data and outputs the same. The other readout circuits, selectors and output circuits have a similar structure and operation.
The readout circuits and memory cell array shown in FIG. 23 will be described in detail hereinafter with reference to FIG. 24. Although a readout circuit RR0a and a memory cell array M0a are shown in FIG. 24, the other readout circuits and memory cell arrays have a similar structure and operate in a similar manner.
Referring to FIG. 24, a memory cell array M0a includes capacitors C41-C44 and transistors Q41-Q44 which are N type MOSFETs to form memory cells, sense amplifiers (SA) SA0-SA3, transfer gates Q31-Q38 formed of N type MOSFETs, word lines WLia and WLib, bit lines BL0-BL3, BL0-/BL3 ("/" indicates a complementary signal line or signal), and a column select line CSLi. For the sake of simplification, the memory cell, the word line, the bit line, and the column select line are shown only partially in FIG. 24.
The gate of transistor Q41 is connected to word line WLia. Transistor Q41 is connected to bit line B20 and capacitor C41. The other capacitors C42-C44 and transistors Q42-Q44 are connected in a similar manner.
Bit lines BL0 and/BL0 are connected to sense amplifier SA0. Sense amplifier SA0 is connected to data input and output lines IO0,/IO0 via transfer gates Q31 and Q32. The other sense amplifiers SA1-SA3 are connected in a similar manner.
Transfer gates Q31-Q38 have their gates connected to column select line CSLi.
According to the above-described structure, data in a memory cell connected to a selected word line and bit line is amplified by a sense amplifier to be output to a data input and output line via a transfer gate.
Next, readout circuit RR0a will be described. Referring to FIG. 24, a readout circuit RR0a includes differential amplifiers (AMP) DA0-DA3, AND gates G61-G64, and transistors Q21-Q28 which are N type MOSFETs.
Predecode signals Y0, Y7, and a differential amplifier activation signal PAE are applied to AND gate G61. AND gate G61 provides a logical product of respective signals to transistors Q21, Q22, and differential amplifier DA0. Differential amplifier DA0 is connected to data input and output lines IO0, /IO0, and also connected to readout data lines RD0a, /RD0a via transistors Q21 and Q22.
According to the above-described structure, when predecode signals Y0 and Y7, and differential amplifier activation signal PAE all attain an H level (logical high), differential amplifier DA0 amplifies a signal applied via data input and output lines IO0,/IO0 to provide the same to readout data lines RD0a, /RD0a via transistors Q21 and Q22.
The other AND gates G62-G64, transistors Q23-Q28, and differential amplifiers DA1-DA3 are formed in a similar manner, and carry out similar operations.
According to the above-described structure, readout circuit RR0a is selected by predecode signal Y7, and differential amplifiers DA0-DA3 selected by predecode signals Y0-Y3 carry out an amplify operation when differential amplifier activation signal PAE attains an active state. Data output from a memory cell array MA0a is provided to one pair of readout data lines RD0a-RD3a, RD0a-/RD3a. The other readout circuits and memory cell arrays have a similar structure, and operate in a similar manner.
The differential amplifier of FIG. 24 will be described in detail with reference to the circuit diagram of FIG. 25.
Referring to FIG. 25, a differential amplifier DA includes inverters G71-G74, transistors Q51-Q54 which are P type MOSFETs, and transistors Q55-Q57 which are N type MOSFETs.
A data signal input via data input and output lines IO,/IO is applied to the gates of transistors Q55 and Q56. Transistor Q55 is connected to transistors Q57 and Q52. Transistors Q57 is connected to a ground potential. A differential amplifier activation signal PAE is applied to the gate of transistors Q57. Transistor Q52 is connected to a power supply voltage V.sub.cc. The gate of transistor Q52 is connected to a node of transistors Q53 and Q56. Transistor Q51 is connected to transistors Q52 and Q55, and also to power supply voltage V.sub.cc. The gate of transistor Q51 receives differential amplifier activation signal PAE. Inverter G72 is connected to inverter G71 and transistor Q51. Inverter G72 outputs amplified data to readout data line RDI. Transistors Q53, Q54, Q56 and inverters G73, G74 are connected in a similar manner. Inverter G74 outputs amplified data to output data line/RDi.
According to the above-described structure, data of readout data lines RDi and/RDi attain an L level (logical low) when differential amplifier activation signal PAE attains an L level. When differential amplifier activation signal PAE attains an H level, data of readout data line RD attains an L level and data of the complementary readout data line/RD attains an H level when data input and output line IO has a higher potential than complementary data input and output line/IO. When the potential of data input and output line IO is lower than that of data input and output line/IO, data of readout data line RD attains an H level and data of readout data line/RD attains an L level. According to the above-described operation, differential amplifier DA responds to differential amplifier activation signal PAE to amplify a data signal applied from data input and output lines IO, /IO to provide the amplified data to readout data lines RDi and/RDi which are complementary to each other.
The control circuit of FIG. 23 will be described in detail with reference to the block diagram of FIG. 26.
Referring to FIG. 26, a control circuit CCP includes a column access activation signal generation circuit C1, a .phi..sub.R generation circuit RG, a .phi..sub.D and PAE generation circuit DPG, a .phi..sub.C generation circuit CGP, a .phi..sub.T generation circuit TGP, and a .phi..sub.E generation circuit EG.
A row address strobe signal/RAS is applied to column access activation signal generation circuit CEG. Column access activation signal generation circuit CEG responds to row address strobe signal/RAS to output a column access activation signal/CE to .phi..sub.D and PAE generation circuit DPG.
.phi..sub.R generation circuit RG receives a row address strobe signal/RAS. .phi..sub.R generation circuit RG responds to row address strobe signal/RAS to output row address buffer control signal .phi..sub.R to row address buffer RB. Row address buffer RD responds to row address buffer control signal .phi..sub.R to latch and output a row address signal RAi according to an input address signal AD.
Row address strobe signal/RAS and column address strobe signal/CAS are applied to .phi..sub.C generation circuit CGP. .phi..sub.C generation circuit CGP responds to row and column address strobe signals/RAS and/CAS to output a column address buffer circuit signal .phi..sub.CP to column address buffer CB. Column address buffer CB responds to column address buffer control signal .phi..sub.CP to latch a column address signal CAi from an input address signal AD to provide column address signal CAi to .phi..sub.D and PAE generation circuit DPG and predecoder PD.
Column access activation signal/CE and column address signal CAi are applied to .phi..sub.D and PAE generation circuit CPG. .phi..sub.D and PAE generation circuit DPG responds to column access activation signal/CE and column address signal CAi to output differential amplifier activation signal PAE to differential amplifier DA, whereby a data select control signal .phi..sub.D is provided to selector SEP. An address change detection signal ATD is output.
Predecoder PD responds to an input column address signal CAi to output predecode signal Yi to selector SEP.
Differential amplifier DA amplifies data input via data input and output line IOi to output the same to selector SEP via readout data line RDi.
Selector SEP responds to data transfer control signal .phi..sub.D to latch input data, and responds to predecode signal Yi to provide predetermined data from a plurality of data to an output circuit DQP via a readout data bus RBUS.
Column address strobe signal/CAS is applied to .phi..sub.T generation circuit TGP. .phi..sub.T generation circuit TGP delays an input column address strobe signal/CAS to output a data transfer control signal .phi..sub.TP to an output data latch DLP. .phi..sub.E generation circuit EG provides an output buffer activation signal .phi..sub.E to output buffer OBP at a predetermined timing.
Output circuit DQP includes an output data latch DLP and an output buffer OBP. Output data latch DLP responds to data transfer control signal .phi..sub.TP to latch data input via readout data bus RBUS to provide the same to output buffer OBP as output signal OD. Output buffer OBP responds to .phi..sub.E to provide output data Dout according to an applied output signal OD.
According to the above-described structure, data input via data input and output line IOi is output via differential amplifier DA, selector SEP, and output circuit DQP at a predetermined timing.
The row address buffer of FIG. 26 will be described in detail with reference to the circuit diagram of FIG. 27.
Referring to FIG. 27, a row address buffer RB includes a transistor Q61 which is an N type MOSFET, and inverters G81-G83.
Row address buffer control signal .phi..sub.R is applied to the gate of transistor Q61. Transistor Q61 is connected to inverters G81 and G82, which in turn are connected to inverter G83. Inverter G83 outputs a row address signal RAi.
According to the above-described structure, when. column address buffer control signal .phi..sub.R attains an H level, transistor Q61 is turned on, whereby address signal AD is latched by a latch circuit formed of inverters G81-G83 to be output as row address signal RAi.
The .phi..sub.R generation circuit of FIG. 26 will be described in detail with reference to the circuit diagram of FIG. 28.
Referring to FIG. 28, a .phi..sub.R generation circuit RG includes inverters G84-G86, an NOR gate G87, and delay capacitors C51 and C52.
Row address strobe signal/RAS is applied to inverter G84 and NOR gate G87. Inverter G84 is connected to capacitors C51 and C52, and inverter G85. Capacitor C51 has one end connected to power supply voltage V.sub.cc, and capacitor C52 has one end connected to ground potential. Inverter G85 is connected to NOR gate G87. NOR gate G87 is connected to inverter G86. Inverter G86 outputs row address buffer control signal .phi..sub.R.
According to the above-described structure, row address strobe signal/RAS is delayed by a delay circuit formed of inverters G84 and G85 and capacitors C51 and C52. The NOR of the delayed row address strobe signal and former row address strobe signal/RAS is inverted to be output as row address buffer control signal .phi..sub.R.
The column access activation signal generation circuit of FIG. 26 will be described in detail with reference to the circuit diagram of FIG. 29.
Referring to FIG. 29, column access activation signal generation circuit CEG includes inverters G88-G90, an NOR gate G91, and delay capacitors C53 and C54.
Row address strobe signal/RAS is applied to inverter G88 and NOR gate G91. Inverter G88 is connected to inverter G89 and capacitors C53 and C54. Capacitor C53 has one end connected to power supply voltage V.sub.cc, and capacitor C54 has one end connected to ground potential. Inverter G89 is connected to NOR gate G91 which is connected to inverter G90. Inverter G90 outputs column access activation signal/CE.
According to the above-described structure, row address strobe signal/RAS is delayed by a delay circuit formed of inverters G88 and G89 and capacitors C53 and C54. The NOR of the delayed row address strobe signal and former row address strobe signal/RAS is inverted to be output as column access activation signal/CE.
The column address buffer of FIG. 26 will be described in further details with reference to the circuit diagram of FIG. 30.
Referring to FIG. 30, column address buffer CB includes a transistor Q62 which is an N type MOSFET, and inverters G101-G103.
Column address buffer control signal .phi..sub.CP is applied to the gate of transistor Q62. Address signal AD is applied to transistor Q62. Transistor Q62 is connected to inverters G101 and G102. Inverters G101 and G102 are connected to inverter G103. Inverter G103 outputs a column address signal CAi.
According to the above-described structure, when column address buffer activation signal .phi..sub.CP attains an H level, transistor Q62 is turned on, whereby address signal AD is latched by a latch circuit formed of inverters G101-G103 to be output as column address signal CAi.
The .phi..sub.C generation circuit of FIG. 26 will be described in detail with reference to the circuit diagram of FIG. 31.
Referring to FIG. 31, .phi..sub.C generation circuit CGP includes inverters G104-G106, an AND gate G107, an NOR gate G108, and delay capacitors C55 and C56.
Column address strobe signal/CAS is supplied to inverter G104. Inverter G014 is connected to inverter G105 and AND gate G107. Inverter G105 is connected to capacitors C55 and C56, and inverter G106. Capacitor C55 has one end connected to power supply potential V.sub.cc, and capacitor C56 has one end connected to ground potential. Inverter G106 is connected to AND gate G107. Row address strobe signal/RAS is applied to NOR gate G108. AND gate G107 is connected to NOR gate G108. Column address buffer control signal .phi..sub.CP is supplied to NOR gate G108.
According to the above-described structure, column address strobe signal/CAS is inverted by inverter G104. The inverted signal is delayed by a delay circuit formed of inverters G105 and G106, and capacitors C55 and C56. The logical product of the delayed signal and former inverted signal is taken by AND gate G107. The NOR of the output signal of AND gate G107 and row address strobe signal/RAS is output as column address buffer control signal .phi..sub.C.
The .phi..sub.T generation circuit of FIG. 26 will be described in detail with reference to the circuit diagram of FIG. 32.
Referring to FIG. 32, .phi..sub.T generation circuit TGP includes inverters G109-G111, and delay capacitors C57 and G58.
Column address strobe signal/CAS is supplied to inverter G109. Inverter 109 is connected to capacitors C57 and C58, and inverter G110. Capacitor C57 has one end connected to power supply voltage V.sub.cc. Capacitor C58 has one end connected to ground potential. Inverter G110 is connected to inverter G111. Inverter G111 outputs data transfer control signal .phi..sub.TP.
According to the above-described structure, column address strobe signal/CAS is delayed by a delay circuit formed of inverters G109 and G110 and capacitor C57 and C57. The delayed signal is inverted by inverter G111 to be output as data transfer control signal .phi..sub.T.
The .phi..sub.D and PAE generation circuit of FIG. 26 will be described in detail with reference to the circuit diagram of FIG. 33.
Referring to FIG. 33, .phi..sub.D and PAE generation circuit DPG includes column address change detection circuits (CAT) CAT0-CATn, inverters G112-G120, an AND gate G121, NAND gates G122, G123, NOR gate G123, delay capacitors C61-C66, and an S-R flipflop SRF.
Corresponding column address signals CA0-CAn are applied to column address change detection circuits CAT0-CATn. Column address change detection circuits CAT0-CATn detect the change of column address signal CA0-CAn to output column address signal change detection signals CAT0-CATn to NOR gate G124. Column access activation signal/CE is applied to NOR gate G124. NOR gate G124 is connected to inverter G112. NOR gate G124 provides to inverter G112 the NOR of column access activation signal CE and column address signal change detection signals CAT0-CATn. Inverter G112 is connected to a set terminal S of S-R flipflop SRF and inverter G113. The output signal of inverter G112 is provided as address change detection signal ATD.
Inverter G113 is connected to AND gate G121. An output terminal Q of S-R flipflop SRF is connected to AND gate G121. AND gate G121 provides differential amplifier activation signal PAE.
Inverter G113 is connected to NAND gate 122. An output terminal Q of S-R flipflop SRF is connected to NAND gates G122 and G123. AND gate G122 is connected to capacitors C65 and C66, and inverter G118. Capacitor C65 has one end connected to power supply voltage V.sub.cc, and capacitor C66 has one end connected to ground potential. Inverter G118 is connected to inverter G117 which is connected to capacitors C63 and C64, and inverter G116. Capacitor C63 has one end connected to power supply voltage V.phi..sub.C, and capacitor C64 has one end connected to ground potential. Inverter G116 is connected to inverters G115 and G119. Inverter G115 is connected to capacitors C61 and C62, and inverter G114. Capacitor C61 has one end connected to power supply voltage V.sub.cc, and capacitor C62 has one end connected to ground potential. Inverter G114 is connected to a reset terminal R of S-R flipflop SRF. Inverter G114 is connected to NAND gate G123. NAND gate G123 is connected to inverter G120. Inverter G120 outputs data select control signal .phi..sub.D.
The operation of the above .phi..sub.D and PAE generation circuit will be described hereinafter. At the elapse of a predetermined time from row address strobe signal/RAS attaining an L level, column access activation signal/CE of an L level is output from column access activation signal generation circuit CEG. When at least one column address signal CAi changes after column access activation signal/CE attains an L level, a corresponding column address signal change detection signal CATi attains an H level for a predetermined time period. As a result, address change detection signal ATD is output at an H level for a predetermined time period.
When address change detection signal ATD attains an H level, output signal Q of S-R flipflop SRF is pulled up to an H level. Then, at the elapse of a predetermined time after address change detection signal ATD attains an L level, the output signal of inverter G114 attains an H level. Here, output signal Q of S-R flipflop SRF is reset to an L level. Therefore, differential amplifier activation signal PAE which is an AND signal of an inverted signal of address change detection signal ATD and output signal Q of S-R flipflop SRF attains an H level at the elapse of a predetermined time after address change detection signal ATD attains an L level.
Furthermore, row address buffer control signal .phi..sub.D attains an H level delayed by the delay time of NAND gate G123 and inverter G120 after address change detection signal ATD attains an H level. Therefore, data select control signal .phi..sub.D is pulled down to an L level earlier by a delay time of inverters G114 and G115 and capacitors C61 and C62 than differential amplifier activation signal PAE attaining an L level.
According to the above operation, .phi..sub.D and PAE generation circuit DPG responds to column access activation signal/CE and column address signals CA0-CAn to output address change detection signal ATD, differential amplifier activation signal PAE, and data select control signal .phi..sub.D.
The column address change detection circuit of FIG. 33 will be described in further detail with reference to the circuit diagram of FIG. 34.
Referring to FIG. 34, column address change detection circuit CAT includes inverters G131-G134, NAND gates G135, G137, and an NOR gate G136. Column address signal CAi is applied to inverter G131 and NOR gate G136. Inverter G131 is connected to inverter G132, and to capacitors C67 and C68. Capacitor C67 has one end connected to power supply voltage V.phi..sub.cc, and capacitor C68 has one end connected to ground potential. Inverter G132 is connected to inverter G133. Inverter G133 is connected to NAND gate G135 and NOR gate G136. NAND gate G135 is connected to NAND gate G137. NOR gate G136 is connected to inverter G134 which is connected to NAND gate G137. NAND gate G137 outputs column address signal change detection signal CATi.
According to the above structure, column address change detection circuit CAT provides column address signal change detection signal CATi of an H level for a predetermined time period when column address signal CAi changes.
The selector SEP of FIG. 26 will be described in further detail with reference to the circuit diagram of FIG. 35.
Referring to FIG. 35, selector SEP includes transistors Q61-Q70 which are N type MOSFETs, and inverters G141-G148.
Predecode signal Y0 is supplied to the gates of transistors Q61 and Q62. Readout data line RD0 is connected to transistor Q69 via transistor Q61. Readout data line/RD0 complementary to readout data line RD0 is connected to transistor Q70 via transistor Q62. Similarly, readout data lines RD1-RD3, /RD1-RD3 are connected to transistors Q69 and Q70 via transistors Q63-Q68, respectively. Data select control signal .phi..sub.D is applied to the gates of transistors Q69 and Q70. Transistor Q69 is connected to inverters G141 and G142. Inverters G141 and G142 are connected to inverter G143. Inverter G143 is connected to inverter G144. Inverter G144 provides an output signal to readout data bus RBUS. Inverters G145-G148 are connected in a similar manner, and inverter G148 provides an output signal to readout data bus/RBUS complementary to readout data bus RBUS.
According to the above-described structure, a signal output from differential amplifier DA via readout data lines RD0-RD3,/RD0-/RD3 is selected by predecode signals Y0-Y3. The selected signal is entered into a latch circuit formed of inverters G141 and G142 and inverters G145 and G146 while data select control signal .phi.T attains an H level. The entered signal is inverted to be output to readout data buses RBUS, /RBUS via inverters G143 and G144, and inverters G147 and G148.
The output data latch and output buffer shown in FIG.. 26 will be described in further detail with reference to the circuit diagram of FIG. 36.
Referring to FIG. 36, output data latch DLP includes transistors Q71-Q74 which are N type MOSFETs and inverters G151-G156.
Data transfer control signal .phi..sub.TP is supplied to the gates of transistors Q71 and Q72. Inverters G151 and G152 are connected to readout data bus RBUS via transistor Q71. Inverters G151 and G152 are connected to transistor Q73. Transistor Q73 has one end connected to ground potential. A predetermined reset signal .phi..sub.RE is supplied to the gate of transistor Q73. Inverters G151 and G152 are connected to inverter G153. Inverter G153 provides an output signal 0D to output buffer OBP. Transistors Q72, Q74 and inverters G154-G156 are connected in a similar manner, whereby an output signal/OD complementary to output signal OD is provided to output buffer OBP.
According to the above-described structure, data of readout data buses RBUS,/RBUS are transferred to latch circuits formed of inverters G151-G153, inverters G154-G156 while data transfer control signal .phi..sub.TP attains an H level to be provided to output buffer OBP as output signals OD, /OD.
The output buffer OBP will be described hereinafter. Referring to FIG. 36, output buffer OBP includes transistors Q75-Q78 which are N type MOSFETs, a transistor Q79 which is a P type MOSFET, a capacitor C71, inverters G159, G160, and NAND gates G157 and G158.
Output buffer activation signal .phi..sub.E is applied to NAND gates G157 and G158. Output signal OD is applied to NAND gate G157. NAND gate G157 is connected to inverter G159 and the gates of transistors Q79 and Q76. Inverter G159 is connected to capacitor C71. Capacitor C71 is connected to transistor Q75 and transistor Q79. Transistor Q75 has one end connected to power supply voltage V.phi..sub.cc, and transistor Q75 has its gate connected to power supply voltage V.sub.cc. Transistor Q79 is connected to transistor Q76, and to the gate of transistor Q77. Transistor Q76 has one end connected to ground potential. Transistor Q77 is connected to power supply voltage V.sub.cc and transistor Q78.
Output signal/OD is supplied to NAND gate G158. NAND gate G158 is connected to inverter G160. Inverter G160 is connected to the gate of transistor Q78. Transistor Q78 has one end connected to ground potential. Output data Dout is provided from a node of transistors Q77 and Q78.
According to the above-described structure, output signals OD,/OD provided from output data latch DLP are output as output data Dout to an output pin while output buffer activation signal .phi..sub.E attains an H level.
The operation of the above-structured semiconductor memory device will be described hereinafter with reference to the first timing chart of FIG. 37.
Referring to FIG. 37, when row address strobe signal RAS attains an L level at time t1, row address signal R1 of address signal AD is ascertained. Then, when column address strobe signal/CAS attains an L level at time t2, column address signal C2 of address signal AD is ascertained. In response to the ascertained row and column address signals, predetermined data is read out from a memory cell, whereby output data D1 is provided at time t4. The subsequent CAS cycle operates in a similar manner.
Another operation of the semiconductor memory device of FIG. 23 will be described with reference to the second timing chart of FIG. 38.
Referring to FIG. 38, when row address strobe signal RAS attains an L level at time t1, row address signal R1 of address signal AD is ascertained. Then, when column address signal C1 of address signal AD is ascertained at time t2, output data D1 is provided at time t4 which is an elapse of an access time t.sub.AA from time t2 when column address signal C1 was ascertained. Then, when column address strobe signal/CAS attains an H level at time t5, column address signal C2 is ascertained, and output data D2 is provided at time t7 which is an elapse of an access time t.sub.CPA from time t5. The subsequent CAS cycle operates in a similar manner.
A conventional semiconductor memory device of the above-described structure had the following problems when the data readout operation is speeded.
First, when the cycle time period of a readout operation is reduced, the time period of column address signal/CAS attaining an L level becomes shorter, resulting in problems set forth in the following. The case where data of an H level is read out will be described first. FIG. 39 is a first timing chart for describing the problems of the semiconductor memory device shown in FIG. 23.
Referring to FIG. 39, at time t1, when column address strobe signal/CAS attains an L level, address signal AD is ascertained. Then, at time t2, column address signal CAi is ascertained. At time t3, predecode signal Yi is ascertained. Then, at time t4, address change detection signal ATD attains an H level. When address change detection signal ATD attains an L level at time t6, differential amplifier activation signal PAE is pulled up to an H level. This causes differential amplifier DA selected by predecode signal Yi to output a signal of an L level to readout data line RDI at time t8.
At time t6, a signal of an L level is transmitted to readout data bus RBS since data select control signal .phi..sub.D of selector SEP attains an H level. However, since column address strobe signal/CAS attains an H level at time t6, column address buffer control signal .phi..sub.CP is pulled up to an H level at time t7. As a result, transistor Q62 of column address buffer CB of FIG. 30 is turned on, and column address signal CAi changes at time t8. This change of column address signal CAi causes change of predecode signal Yi at time t9. Therefore, at time t9 prior to time t10 where data select control signal .phi..sub.D of selector SEP attains an L level, differential amplifier activation signal PAE of differential amplifier DA previously selected by predecode signal Yi attains an L level. As a result, the data in the latch circuit (inverters G141 and G142, and inverters G145 and G146) of selector SEP is lost, whereby the signal of readout data bus RBUS is pulled down to an L level. Therefore, output buffer OBP attains a high impedance state since both output signals OD and/OD of output data latch OBP attain an L level.
It is necessary to set the period of column address strobe signal/CAS attaining an H level shorter than the same attaining an L level since the time period of column address strobe signal/CAS attaining an L level cannot be made shorter. Furthermore, if the cycle time period of column address strobe signal/CAS is reduced to comply with an increase of speed of the semiconductor memory device, the time period of column address strobe signal CAS attaining an H level is extremely short. In order to propagate a short pulse waveform on a printed circuit board, it is necessary to reduce the capacitive coupling of the wiring. An expensive multilayer substrate had to be used to reduce the length of the wiring.
After time t6 when column address strobe signal/CAS attains an H level, if the delay time starting from column address buffer control signal .phi..sub.C attaining an H level until an address signal AD is entered at time t7 is too long, address signal AD will not be entered even when column address strobe signal/CAS attains an H level. Therefore, as shown in the timing chart of FIG. 38, there was the problem that the access time t.sub.CPA subsequent to column address strobe signal/CAS attaining an H level is delayed even when address signal AD is applied at a constant cycle.
It was also difficult to improve the access time when data of an H level is read out continuously in a conventional semiconductor memory device due to the following problem. This second problem is described with reference to a timing chart of FIG. 40.
Referring to FIG. 40, at time t1, when an address signal AD is entered, differential amplifier activation signal PAE attains an H level at time t7 as in the above-described case. Then, at time t8, data of readout data lines RDi and/RDi are transferred to output data latch DLP via selector SEP and readout data bus RBUS, whereby output signal OD of output data latch DLP attains an H level. Here, in output buffer OBP, the potential of capacitor C71 precharged to the level of V.sub.cc -V.sub.th (V.sub.th is the transistor threshold voltage) by transistor Q75 is further boosted by an output signal of inverter G159 to attain the level of 2V.sub.cc -V.sub.th. Simultaneously, transistor Q79 is rendered conductive, whereby the gate potential of transistor Q77 attains the level of 2V.sub.cc -V.sub.th. Therefore, output data Dout of output buffer OBP speedily attains the level of V.sub.cc, whereby data of an H level is output. When data of an H level is to be read out also at the next cycle, following entry of an address signal AD at time t12, differential amplifier activation signal PAE attains an H level at time t17. At time t18, data of readout data lines RDi, /RDi are transferred to output data latch TLP via selector SEP and readout data bus RBUS.
The level of a standby state of differential amplifier DA is transmitted to output data latch DLP since data transfer control signal .phi..sub.TP attains an H level at time t17. As a result, the output signal of NAND gate G157 attains an H level since output signals OD and/OD of output data latch DLP attains an L level. Therefore, transistor Q76 conducts, whereby the ground potential of transistor Q77 temporarily attains a ground potential. In order to output data of an H level again at time t18, it is necessary to boost the gate potential of transistor Q77 to the level of 2V.sub.cc -V.sub.th again. Capacitor C71 must be rapidly charged to the level of V.sub.cc-V.sub.th during the short time period from time t17 to time t18. However, capacitor C71 cannot be rapidly charged in such a short time period from time t17 to t18. The gate potential of transistor Q77 could not be boosted sufficiently, resulting in the problem of reduction in the output level of output buffer OBP. Therefore, it is therefore necessary to pull data transfer control signal .phi..sub.T to a level of H at time t19 after output signal RDi of differential amplifier DA attains an L level at time t18. Thus, the time for an output signal RDi of differential amplifier DA arriving at output data latch DLP via selector SEP and readout data bus RBUS is retarded, resulting in a problem that the access time is delayed.
In order to achieve high speed operation in a conventional semiconductor memory device, the column address change detection circuit of FIG. 34 is operated at high speed. Noise in an input address signal AD, even a short noise, will be propagated to address change detection signal ATD. This third problem will be described hereinafter in the case of reading out data of an H level according to a third timing chart of FIG. 41.
Referring to FIG. 41, when address signal AD is applied at time t1, address change detection signal ATD and data select control signal .phi..sub.T attain an H level at time t2. When address change detection signal ATD attains an L level at time t3, differential amplifier activation signal PAE attains an H level. At time t4 when readout data RD attains an L level, data of readout data line RD is transferred to readout data bus RBUS since data select control signal .phi..sub.D attains an H level.
At time t7 when noise is included in address signal AD, the noise is transmitted to address change detection signal ATD at time t8. Noise is generated also in data select control signal .phi..sub.D. S-R flipflop SRF of the .phi..sub.D and PAE generation circuit RPG shown in FIG. 32 is not completely inverted. Therefore, when there is no noise at time t9, the output signal of S-R flipflop SRF attains an L level. Therefore, differential amplifier activation signal PAE is left at an L level. At time t8 when noise is included in data select control signal .phi..sub.D and an output signal of differential amplifier DA is transmitted to readout data line RD at an inactivated state, differential amplifier DA will not attain an activation state thereafter. Therefore, data of readout data bus RBUS will remain lost. When column address strobe signal/CAS attains an L level at time t10, output buffer activation signal .phi..sub.E attains an H level at time t11. Even when data transfer control signal .phi..sub.T attains an H level at time t12, readout data buses RBUS and/RBUS attain an L level, so that output data Dout is held at a high impedance state. Thus, there was the problem that high speed operation cannot be realized.